Semiconductor memories generally employ internal voltages for conducting their internal operations, based on power voltages (VDD) and ground voltages (VSS) supplied thereto from external systems. There are various types of voltages necessary for internal operations of the semiconductor memories, such as core voltage (Vcore) supplied into a memory core region, high voltage or pumping voltage (VPP) used in driving or over-driving word lines, back-bias voltage provided for a bulk region for NMOS transistors of the core region, and peripheral voltage (VPERI; hereinafter referred to as “peri-voltage”) supplied into a peripheral region where control circuits of the semiconductor memories are disposed.
Meanwhile, semiconductor memories are normally configured to reduce a rate of power dissipation by generating and utilizing internal voltages that are lowered in standby modes, in which commands are waiting to be conducted, than in active modes in which reading and writing operations are carried out. For example, the peri-voltage is designed to be at a target level of 1.8V in the active mode, and to be at 1.2V in the standby mode so as to reduce power consumption.
FIG. 1 is a block diagram of a conventional peri-voltage generation circuit.
As shown in FIG. 1, the general peri-voltage generation circuit is formed of an active internal voltage generator 10 supplying 1.8V as a target level of the peri-voltage VPERI for the active mode, and a standby internal voltage generator 12 supplying 1.2V as a target level of the peri-voltage VPERI for the standby mode. For the purpose of providing the pen-voltage to the target levels, the active and standby internal voltage generators, 10 and 12, are formed of comparators (not shown) each receiving reference voltages of predetermined levels and driving the peri-voltage to the target levels.
The conventional peri-voltage generation circuit with such a configuration operates as follows.
First, in the standby mode, the standby internal voltage generator 12 generates the peri-voltage VPERI to the target level 1.2V in response to an active signal ACT that is disabled. Then, the active signal ACT enabled by an active command stops driving the standby internal voltage generator 12, and begins driving the active internal voltage generator 10 to raise the peri-voltage VPERI up to 1.8V, which is the target level of the active mode, from 1.2V of the standby mode.
However, as the peri-voltage VPERI is driven by the comparator (not shown) of the active internal voltage generator 10 while turning an operation mode from the standby mode to the active mode, it takes much time to raise the peri-voltage VPERI up to the active mode target level 1.8V from 1.2V. Further, while the peri-voltage VPERI is driven to the target level, leakage current could flow through the standby internal voltage generator 12 that has been shut off in operation, causing power dissipation.